One is a FPGA-based CPU core. It is also a system consisting of the one CPU along with a small number of surrounding peripherals.
It is in an early stage of design.
Here are a few notes on the instruction set.
Instruction set concepts
ld rx, (ry + k) st rx, (ry + k) add rx, ry, rz mov rx, ry ld rx, #123 b (rx + k) bl (rx + k) load/store ld rx, (ry + k) ld rx, (++ry + k) [aka pop] st rx, (ry + k) st rx, (ry-- + k) [aka push] ld rx, #k Is this really a mov? branch b[cond] (ry + k) bl[cond] (ry + k) ALU op alu3[op] rx, ry, rz [ux, uy] alu3[op] rx, ry, #k [ux, uy] alu2[op] rx, ry [ux, uy] alu2[op] rx, #k [ux] (this is the same as ld (7), or compare) trap ? trap rx trap #k
8 registers (including PC)
flags (not mapped into register file)
Instruction set
| f | e | d | c | b | a | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| f | e | d | c | b | a | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| add | 0 | 0 | 0 | 0 | k | ry | rx | ||||||||||
| adc | 0 | 0 | 0 | 1 | k | ry | rx | ||||||||||
| rsb | 0 | 0 | 1 | 0 | k | ry | rx | ||||||||||
| rsbc | 0 | 0 | 1 | 1 | k | ry | rx | ||||||||||
| and | 0 | 1 | 0 | 0 | k | ry | rx | ||||||||||
| or | 0 | 1 | 0 | 1 | k | ry | rx | ||||||||||
| xor | 0 | 1 | 1 | 0 | k | ry | rx | ||||||||||
| mul | 0 | 1 | 1 | 1 | k | ry | rx | ext=0 | |||||||||
| smul | 0 | 1 | 1 | 1 | k | ry | rx | ext=1 | |||||||||
| div | 0 | 1 | 1 | 1 | k | ry | rx | ext=2 | |||||||||
| sdiv | 0 | 1 | 1 | 1 | k | ry | rx | ext=3 | |||||||||
| ld | 1 | 0 | 0 | 0 | k | ry | rx | ext=0 32-bit ext=1 16-bit ext=2 8-bit |
|||||||||
| st | 1 | 0 | 0 | 1 | k | ry | rx | ||||||||||
| b | 1 | 0 | 1 | 0 | k | ry | cond | ||||||||||
| bl | 1 | 0 | 1 | 1 | k | ry | cond | ||||||||||
| add | 1 | 1 | 0 | 0 | 0 | 0 | 0 | rz | ry | rx | |||||||
| adc | 1 | 1 | 0 | 0 | 0 | 0 | 1 | rz | ry | rx | |||||||
| rsb | 1 | 1 | 0 | 0 | 0 | 1 | 0 | rz | ry | rx | |||||||
| rsbc | 1 | 1 | 0 | 0 | 0 | 1 | 1 | rz | ry | rx | |||||||
| and | 1 | 1 | 0 | 0 | 1 | 0 | 0 | rz | ry | rx | |||||||
| or | 1 | 1 | 0 | 0 | 1 | 0 | 1 | rz | ry | rx | |||||||
| xor | 1 | 1 | 0 | 0 | 1 | 1 | 0 | rz | ry | rx | |||||||
| mul | 1 | 1 | 0 | 0 | 1 | 1 | 1 | rz | ry | rx | ext=0 | ||||||
| smul | 1 | 1 | 0 | 0 | 1 | 1 | 1 | rz | ry | rx | ext=1 | ||||||
| div | 1 | 1 | 0 | 0 | 1 | 1 | 1 | rz | ry | rx | ext=2 | ||||||
| sdiv | 1 | 1 | 0 | 0 | 1 | 1 | 1 | rz | ry | rx | ext=3 | ||||||
| ld | 1 | 1 | 0 | 1 | k | rx | |||||||||||
| prfx | 1 | 1 | 1 | 0 | k | ||||||||||||
| ror | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | k | rx | |||||||
| rol | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | k | rx | |||||||
| lsl | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | k | rx | |||||||
| lsr | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | k | rx | |||||||
| mov | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | ux | uy | ry | rx | iy rx is pc, ux means rti | ||||
| ror | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | k | rx | 32-bit | ||||
| rol | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | k | rx | |||||
| lsl | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | k | rx | |||||
| lsr | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | k | rx | |||||
| push | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | ry | rx | |||||
| pop | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | ry | rx | |||||
| ror | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | ry | rx | 16-bit | ||||
| rol | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | ry | rx | |||||
| sxt | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | ry | rx | sign-extend | ||||
| mov | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | rx | read flags | ||
| mov | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | rx | write flags | ||
| cfl | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | fln | write flags | ||
| sfl | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | fln | write flags | ||
| alt | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | ext | set ext for next instruction (alternate instruction prefix) | ||
| spre | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | ? | |||
| spre | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | ? | ||||
| spre | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | ? | |||||||
| ror | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | k | rx | 16-bit | |||||
| rol | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | k | rx | ||||||
| spre | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | ? | ||||||||
| spre | 1 | 1 | 1 | 1 | 1 | 0 | 1 | ? | |||||||||
| spre | 1 | 1 | 1 | 1 | 1 | 1 | ? | ||||||||||
Special purpose intsructions
These are special purpose interpretations of more general forms of instruction.
bs = byte-swap swp = atomically swap *rx and *ry rti = mov, but also return to user mode. Destination is usually the program counter. mov upc, rx = rti mov upc, urx = mov rx, upc = trap mov urx, upc = mov upc, upc = mov urx, ury = bswap
prefix alternate instruction set
mul => div
signed div
signed mul
rotate => rotate 16 bits
load/store => byte
half-word