I decided to have a play around with digital hardware. Having been exposed to some verilog at work, and seen that FPGA development boards have become quite affordable, I thought I’d have a go.
So I installed Icarus Verilog (an open-source verilog compiler and simulator) and gtkwave (an open-source waveform viewer) and started playing.
The first thing I tried was a simple binary counter. This is, I guess, the hardware equivalent of a “Hello, World!” program. It worked great as a way of proving the toolchain to the point of being able to display a waveform. Being new to verilog, it took a few attempts to figure out how to convince the simulator to actually output something that gtkwave could read, but once I’d got that sorted it worked great.
So I thought I’d try a simple ALU. I imagined that it would involve a bit of effort, but after about 10 lines of code it seemed that it was sufficient. I spent some time writing a test harness in order to provide sample input and to be able to see the waveforms, and lo and behold, it worked.
Of course, this is all still on a simulator.
The next thing I tried was to implement a noddy CPU. I chose 16-bit registers, 16-bit instruction words, a 16-bit address bus and a 16-bit data bus. It seemed to make sense to keep it simple like that. The CPU was a simple state machine. This took a little bit more effort to code in Verilog, but still turned out to be relatively straightforward. I didn’t try to implement pipelining. There were four general purpose registers, and a program counter. I chose three classes of instructions – ALU operations, load/store, and branch.
The test harness consisted of a “RAM” interface, and a program preloaded into RAM.
Amazingly, it worked.
At this stage I’d not implemented conditional branches, and flags. So I added in the code for these, and was then able to write a test program which involved a loop – adding up all the numbers from 1 to 10. Watching it perform a loop on the simulator for the first time was wonderful.
Now, this isn’t going to win any prizes for hardware design. It’s a toy CPU. But it works, and that makes me happy.
In the meantime, I downloaded and installed Xilinx WebPACK, their free (if rather huge) design tools. I ran my code through their synthesizer, since code which could simulate isn’t necessary viable in real hardware. With some minor adjustments, that worked too. Sadly I don’t have an FPGA development board yet, but I’m looking forward to trying this out in real hardware when I get one.