one

Sat, Aug 29, 2009 in Project using tags cpu , fpga , incomplete

One is a FPGA-based CPU core. It is also a system consisting of the one CPU along with a small number of surrounding peripherals.

It is in an early stage of design.

Here are a few notes on the instruction set.

Instruction set concepts

ld rx, (ry + k)
st rx, (ry + k)

add rx, ry, rz
mov rx, ry

ld rx, #123

b (rx + k)
bl (rx + k)

load/store
	ld rx, (ry + k)
	ld rx, (++ry + k) [aka pop]
	st rx, (ry + k)
	st rx, (ry-- + k) [aka push]
	ld rx, #k		Is this really a mov?
branch
	b[cond] (ry + k)
	bl[cond] (ry + k)
ALU op
	alu3[op] rx, ry, rz [ux, uy]
	alu3[op] rx, ry, #k [ux, uy]
	alu2[op] rx, ry [ux, uy]
	alu2[op] rx, #k [ux] (this is the same as ld (7), or compare)
trap
?	trap rx
	trap #k

8 registers (including PC) flags (not mapped into register file)

Instruction set

fedcba9876543210
fedcba9876543210
add0000kryrx
adc0001kryrx
rsb0010kryrx
rsbc0011kryrx
and0100kryrx
or0101kryrx
xor0110kryrx
mul0111kryrxext=0
smul0111kryrxext=1
div0111kryrxext=2
sdiv0111kryrxext=3
ld1000kryrxext=0 32-bit
ext=1 16-bit
ext=2 8-bit
st1001kryrx
b1010krycond
bl1011krycond
add1100000rzryrx
adc1100001rzryrx
rsb1100010rzryrx
rsbc1100011rzryrx
and1100100rzryrx
or1100101rzryrx
xor1100110rzryrx
mul1100111rzryrxext=0
smul1100111rzryrxext=1
div1100111rzryrxext=2
sdiv1100111rzryrxext=3
ld1101krx
prfx1110k
ror11110000krx
rol11110001krx
lsl11110010krx
lsr11110011krx
mov11110100uxuyryrxiy rx is pc, ux means rti
ror1111010100krx32-bit
rol1111010101krx
lsl1111010110krx
lsr1111010111krx
push1111011000ryrx
pop1111011001ryrx
ror1111011010ryrx16-bit
rol1111011011ryrx
sxt1111011100ryrxsign-extend
mov1111011101000rxread flags
mov1111011101001rxwrite flags
cfl1111011101010flnwrite flags
sfl1111011101011flnwrite flags
alt1111011101100extset ext for next instruction (alternate instruction prefix)
spre1111011101101?
spre111101110111?
spre111101111?
ror111110000krx16-bit
rol111110001krx
spre11111001?
spre1111101?
spre111111?

Special purpose intsructions

These are special purpose interpretations of more general forms of instruction.

bs = byte-swap
swp = atomically swap *rx and *ry
rti = mov, but also return to user mode. Destination is usually the program counter.

mov upc, rx        = rti
mov upc, urx       = 
mov rx, upc        = trap
mov urx, upc       =
mov upc, upc       =
mov urx, ury       = bswap
prefix alternate instruction set
    mul => div
	   signed div
	   signed mul
    rotate => rotate 16 bits
    load/store => byte
		  half-word